The MMU
An official overview of the ARMv8 MMU is published by ARM at
arm.com.
The ARMv8 MMU has two base registers for address translation
TTBR0_EL1 & TTBR1_El1 which point to the first level translation tables for
lower and higher half address respectively. It supports up to four table
levels with a maximum address space of up to 48 bits. Configuration is
controlled through TCR_EL1 and MAIR_EL1 with enable through SCTLR_EL1.
Granule
For a granule size of 4KiB pages every page is indexed by 9 bits for a table
size of 4KiB leaving the required 12 bits for page indexing. Level 1 & 2
tables also support block pointers which allows for larger continuous memory
areas of 1GiB or 2MiB.
Virtual address layout
| 63:48 |
47:39 |
38:30 |
29:21 |
20:12 |
11:0 |
| Reserved |
L0 Index |
L1 Index |
L2 Index |
L3 Index |
Page index |
| - |
L1 Table |
L2 Table |
L3 Table |
- |
- |
| - |
- |
1GiB Block |
2MiB Block |
4KiB Page |
- |
Table entries
The following descriptor formats are valid for a 4KiB granule and 48 bit OA.
A full description is available in ARM document DDI0487 chapter D8.3.
Table Descriptor (L0, L1, L2)
| 63:59 |
58:51 |
50:48 |
47:12 |
11:2 |
1 |
0 |
| Attributes |
Ignored |
Reserved 0 |
Table address |
Ignored |
1 |
1 |
Block Descriptor (L1)
| 63:50 |
49:48 |
47:30 |
29:17 |
16 |
15:12 |
11:2 |
1 |
0 |
| Upper attributes |
Reserved 0 |
Output address |
Reserved 0 |
nT |
Reserved 0 |
Lower attributes |
0 |
1 |
Block Descriptor (L2)
| 63:50 |
49:48 |
47:21 |
20:17 |
16 |
15:12 |
11:2 |
1 |
0 |
| Upper attributes |
Reserved 0 |
Output address |
Reserved 0 |
nT |
Reserved 0 |
Lower attributes |
0 |
1 |
Page Descriptor (L3)
| 63:50 |
49:48 |
47:12 |
11:2 |
1 |
0 |
| Upper attributes |
Reserved 0 |
Output address |
Lower attributes |
1 |
1 |
Invalid Descriptor